Storage Chip Market: Multiple Forces Driving Growth – DDR4 Continues to Thrive, NAND and Next – Generation Technologies Accelerate Iteration
Recently, the storage chip market has shown a multi – dimensional active trend. The strong demand for DDR4 has driven up prices, NAND Flash is accelerating technological iteration and structural adjustment, Samsung has made technological upgrades in the HBM field, and DDR6 has entered the stage of mass production preparation. All these together outline a distinct picture of the industry’s supply – demand changes and technological evolution.
The DDR4 market has entered a golden period of rising both volume and price. Since May, the spot price of DDR4 has increased significantly, contract price negotiations have shifted to a seller’s market. From the third quarter, the quotations of related product lines have risen, the demand for orders is strong, and the operating momentum will continue to pick up in the second half of the year. The 8GB and 16GB DDR4 products of Winbond have seen prominent price increases, among which the 8GB DDR4 has started to have a large output in the second half of the year. At present, DDR4 and LPDDR4 are in high demand, and the market visibility has extended to the fourth quarter. In terms of production capacity, mainstream DDR4 adopts 20 – nanometer technology, which is still competitive; the next – generation 16 – nanometer technology is expected to have a large output in the first to second quarter of 2026. As some original manufacturers withdraw from the DDR4 market, the supply – demand gap is expected to last for 1 – 2 years. Since the entry – level capacity of DDR5 is 16GB, it is more cost – effective for non – PC and non – mobile consumer products to be equipped with DDR4. Under the situation of short supply, the quotation advantage of DDR4 will last for multiple quarters.
The NAND Flash sector is undergoing structural adjustment. Original manufacturers are accelerating the iteration to high – density and large – capacity TLC/QLC. The output of NAND with 256Gb and below capacity has shrunk significantly, some products have been discontinued, and the supply of low – capacity embedded products is becoming tight. The 32GB and below eMMC applications are scattered, covering automotive after – market, smart speakers and other fields. Although high – end models have turned to higher configurations, low – capacity products still have a market. In terms of price, the cumulative increase of 256Gb TLC NAND in half a year is nearly 80%, hitting a four – year high; the price of MLC NAND has doubled compared with the end of last year. The price of 512Gb NAND Wafer is relatively stable, and the price difference between 256Gb and 512Gb TLC has shrunk to 0.3 dollars, driving up the price of embedded finished products. The spot prices of 16GB/32GB/64GB eMMC are already close. The industry predicts that with the consumption of low – capacity inventory, the price of 16GB eMMC may surpass that of 32GB, and suppliers will alleviate the supply problem by downgrading high – capacity products.
Samsung has taken a key step in HBM technology and plans to apply hybrid bonding technology to 16 – layer HBM. When HBM exceeds 16 layers, the existing thermocompression bonding technology is limited. Hybrid bonding can eliminate micro bumps, directly connect DRAM and copper, reduce thickness and achieve better heat dissipation. Samsung plans to adopt both thermocompression and hybrid bonding in the 7th – generation 16 – layer HBM4E, and fully introduce hybrid bonding in the 8th – generation 20 – layer HBM5. At present, the latest commercial product is the 12 – layer HBM3E.
Looking to the future, driven by the demand for generative AI, HPC and data centers, DDR6 has entered the stage of mass production preparation and is expected to be widely introduced in 2027. The three major original manufacturers, Samsung, Micron and SK Hynix, have started development. JEDEC plans to complete the DDR6 specification draft by the end of 2024, release the LPDDR6 draft in the second quarter of 2025, and enter the platform testing phase in 2026. The performance of DDR6 has been significantly improved, with the initial transmission rate reaching 8800MT/s and the maximum reaching 17600MT/s, which is 2 – 3 times higher than that of DDR5. It adopts a 4x24bit sub – channel design, which has better parallel processing efficiency. Traditional slots are difficult to support DDR6, and the CAMM2 architecture solves this limitation through high bandwidth, high density and other characteristics. The next – generation CPU will support DDR6 in 2026, and the global industrial chain is actively module design, packaging technology and other links to seize the opportunity in the high – performance computing market.